Evolution of the semiconductor manufacturing industry is placing greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions continue to shrink, yet the industry needs to decrease time for achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for a semiconductor manufacturer.
Fabricating semiconductor devices, such as logic and memory devices, typically includes processing a semiconductor wafer using a large number of fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a single semiconductor wafer that are separated into individual semiconductor devices.
Inspection processes are used at various steps during semiconductor manufacturing to detect defects on wafers to promote higher yield in the manufacturing process and, thus, higher profits. Inspection has always been an important part of fabricating semiconductor devices such as integrated circuits (ICs). However, as the dimensions of semiconductor devices decrease, inspection becomes even more important to the successful manufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail. For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing size has become necessary because even relatively small defects may cause unwanted aberrations in the semiconductor devices.
As design rules shrink, however, semiconductor manufacturing processes may be operating closer to the limitation on the performance capability of the processes. In addition, smaller defects can have an impact on the electrical parameters of the device as the design rules shrink, which drives more sensitive inspections. As design rules shrink, the population of potentially yield-relevant defects detected by inspection grows dramatically, and the population of nuisance defects detected by inspection also increases dramatically. Therefore, more defects may be detected on the wafers, and correcting the processes to eliminate all of the defects may be difficult and expensive. Determining which of the defects actually have an effect on the electrical parameters of the devices and the yield may allow process control methods to be focused on those defects while largely ignoring others. Furthermore, at smaller design rules, process induced failures, in some cases, tend to be systematic. That is, process-induced failures tend to fail at predetermined design patterns often repeated many times within the design. Elimination of spatially-systematic, electrically-relevant defects can have an impact on yield.
Each new generation of wafer inspection tools brings higher sensitivity and higher throughput. Increasing the throughput requires faster cameras, but also brighter light sources that can place more photons on a wafer in less time. Even if brighter light sources can be produced, such brighter light sources can have reliability or cost drawbacks. The cameras can help with this by increasing the number of time delay integration (TDI) stages (e.g., pixels used to integrate light for a given image) in a sensor. When the number of TDI stages is reached, multiple sensors can be tiled to better utilize the available field of view.
Previously, a single carrier electronics device to support multiple sensors was used. The common carrier approach does not allow for flexible integration of each sensor. Furthermore, alignment is done without live feedback because the camera cannot operate during alignment. This makes operation challenging. There also is a size limit as to how many sensors can be supported using a common carrier.
A detached sensor solution providing pig-tails or flexible media also was previously used. This cabling solution allow independent sensor mechanical manipulation, but does not provide a high-speed solution that can support high throughput camera requirements (e.g., more than 3 million lines per second). The number of connectors that need to be used can result in a larger volume implementation and reliability problems with the connectors.
Therefore, an improved camera for inspection of semiconductor wafers is needed.